Thursday, September 8, 2016

System Verilog Interview Questions Part 1

1.Difference between int and integer.
2.Difference between bit [7:0] and byte.
3.Significance of logic data type?
4.Advantage of using dynamic array?
5.Difference between dynamic array, queue and associative array?
6.Difference between verilog and systemverilog.
7.What is static and dynamic objects in testbench?
8.Why can’t we use interface instead mailbox?
9.What is callback?
10.What is casting? How it works?
11.Explain polymorphism with an example.
12.What is encapsulation?
13.Question regarding stratified event queue how blocking and non-blocking assignments happens in verilog.
14.What is the use of modports?
15.What is input clock skew and output clock skew?
16.Difference between function and task.
17.How to randomize a variable though it is not declared as rand/randc?
18.How this array works arry [*] [$] [ ].
19.features of SV.
20.What is the limitation of randc?
21.Declaring a variable as rand, how to make use of that variable to work as randc.
22.Explain about ignore bins.
23.Explain code coverage.
24. Difference between task and  function?
25. Difference between Final and Initial block?
26. What is Bin?
27. What are void function?
28. What is difference between program and module?
29. What is difference between code coverage and functional coverage?


  1. Tks very much for your post.

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