Tuesday, October 18, 2011

FPGA Interview Questions


1. What is the full form of RTL?
2. What is the difference between RTL and HDL?
3. Draw the state diagram to detect a sequence?
4. Draw the state diagram of a traffic light controller?
5. Which one is faster Carry look ahead or ripple carry adder?
6. What is the difference between Big Endean format and Little Endean format?
7. Can you model SRAM at RTL level?
8. What do you mean by concurrent statement?
9. Define component instantiation?
10. What is the difference between variable and signal?
11. List some sequential statements?
12. Define a test bench?
13. What are the advantages of test benches?
14. What is the difference between behavioral simulation and timing simulation?
15. Does frequency of operation depend on critical path in a circuit? Justify?
16. What is slack?
17. What are different types of scaling? Which one is used and why?
18. What are the different design styles in VLSI?
19. What is the full form of ABEL?
20. What is entry delay and exit delay?
21. What is Controllability and Observability in testing?
22. What is fault coverage?
23. What is DFT? What is its importance?
24. Expand BIST? Explain?
25. What is the difference between testing and verification?
26. Given a circuit with a fault you have to find the test vector to detect that fault?
27. Consider a counter. I want it to sense odd pulses or even pulses (alternate pulses).How will you do it?
28. What is Synthesis?
29. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
30. What’s the critical path in a SRAM?
31. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
32. Draw a 6-T SRAM Cell and explain the Read and Write operations
33. Draw the SRAM Write Circuitry
34. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
35. How will you allocate your time between architecture, coding, and verification?
36. How do you differentiate between coding in C/C++ and at RTL (Register Transfer Level) ?
37. How to implement Half-adder and full-adder in RTL?
38. When the latches are inferred in RTL ?


VLSI FPGA Design & Verification Questions


1. What is FPGA ?
2. What is the significance of FPGAs in modern day electronics?
3. What is Synthesis?
4. FPGA design flow?
5. Tell me some features of FPGA you are currently using?
6. What is LUT?
7. What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
8. Can you explain what ‘stuck at zero’ means?
9. How to generate clocks on FPGA?
10. What are DCM’s? Why they are used?
11. How do you implement DCM?
12. Why is map-timing option used?
13. What are different types of timing verifications?
14. What is FPGA you are currently using and some of main reasons for choosing it?
15. Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?
16. What is LVs and why do we do that. What is the difference between LVS and DRC?
17. What is minimum and maximum frequency of DCM in spartan-3 series fpga?
18. What is the purpose of a constraint file what is its extension?
19. Tell me some of timing constraints you have used?
20. Can you list out some of synthesizable and non synthesizable constructs?
21. When are DFT and Formal verification used?
22. Can you draw general structure of fpga?
23. What are different types of FPGA programming modes?what are you currently using ?how to change from one to another?
24. How many global buffers are there in your current fpga what is their significance?
25. What is gate count of your project?
26. Can you suggest some ways to increase clock frequency?
27. What is the significance of contamination delay in sequential circuit timing?
28. Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is 50,000 will the size of bitmap change? In other words will size of bitmap change it gate count change?
29. What do conditional assignments get inferred into?
30. What are different types of FPGA programming modes? What are you currently using ? How to change from one to another?
31. What logic is inferred when there are multiple assign statements targeting the same wire?
32. Compare PLL & DLL ?
33. How to achieve 180 degree exact phase shift?
34. We need to sample an input or output something at different rates, but I need to vary the rate? What’s a clean way to do this?
35. What is slice? What is CLB?
36. Can a CLB configured as ram?
37. What is the purpose of DRC?
38. What is frequency of operation and equivalent gate count of u r project?
39. What are the differences between FPGA and CPLD?
40. Draw a rough diagram of how clock is routed through out FPGA?
41. What is DFT ?
42. What is FPGA you are currently using and some of main reasons for choosing it?
43. Draw a rough diagram of how clock is routed through out FPGA?
44. What is SOPC Builder?
45. How do you implement the GCLK when there is lack of Source?
46. What are the latest FPGAs you like?Why?
47. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
48. How do you measure the size and density of various programmable logic devices?
49. What is soft processor? What is hard processor?
50. What is meant by 90nm technology?
51. What are the different forms of pull up?
52. What do you mean by translation and mapping?
53. What do you mean by speed grade?
54. What is the difference between ASIC Design and FPGA Design?
55. Setup time and hold time in digital circuits.
56. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
57. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
58. Knowledge of Synthesis and layout constraints.


Saturday, January 15, 2011

Digital design Interview Questions

  • If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
  • Design a circuit to divide input frequency by 2?
  • Design a divide by two counter using D-Latch.
  • Design a divide-by-3 sequential circuit with 50% duty cycle.
  • What are the different types of adder implementation?
  • Draw a Transmission Gate-based D-Latch?
  • Give the truth table for a Half Adder. Give a gate level implementation of the same.
  • Design an OR gate from 2:1 MUX.
  • What is the difference between a LATCH and a FLIP-FLOP?
  • Design a D Flip-Flop from two latches.
  • Design a 2 bit counter using D Flip-Flop.
  • What are the two types of delays in any digital system
  • Design a Transparent Latch using a 2:1 Mux.
  • Design a 4:1 Mux using 2:1 Mux's.
  • What is metastable state? How does it occur?
  • What is metastablity?
  • Design a 3:8 decoder
  • Design a FSM to detect sequence "101" in input sequence
  • Convert NAND gate into Inverter in two different ways.
  • Design a D and T flip flop using 2:1 mux only.
  • Design D Latch from SR flip-flop.
  • Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
  • What is race condition? How it occurs? How to avoid it?
  • Design a 4 bit Gray Counter?
  • Design 4-bit synchronous counter, asynchronous counter?
  • Design a 16 byte asynchronous FIFO?
  • What is the difference between a EEPROM and FLASH?
  • What is the difference between a NAND-based Flash and NOR-based Flash?
  • Which one is good: asynchronous reset or synchronous reset? Why?
  • Design a simple circuit based on combinational logic to double the output frequency.
  • What is the difference between flip-flop and latch?
  • Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < a =" B.">
  • Give two ways of converting a two input NAND gate to an inverter?
  • What is the difference between mealy and moore state-machines?
  • What is the difference between latch based design and flip-flop based design?
  • What is metastability and how to prevent it?
  • Design a four-input NAND gate using only two-input NAND gates.
  • Why are most interrupts active low?
  • How do you detect if two 8-bit signals are same?
  • 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
  • Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
  • How will you implement a full subtractor from a full adder?
  • In a 3-bit Johnson's counter what are the unused states?
  • What is difference between RAM and FIFO?
  • What is an LFSR? List a few of its industry applications.
  • Implement the following circuits:
    (a) 3 input NAND gate using minimum number of 2 input NAND gates
    (b) 3 input NOR gate using minimum number of 2 input NOR gates
    (c) 3 input XNOR gate using minimum number of 2 input XNOR gates assuming 3 inputs A,B,C?
  • Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
  • How to implement a Master Slave flip flop using a 2 to 1 mux?
  • How many 2 input xor's are needed to inplement 16 input parity generator?
  • Convert xor gate to buffer and inverter.
  • Difference between onehot and binary encoding?
  • What are different ways to synchronize between two clock domains?
  • How to calculate maximum operating frequency?
  • How to find out longest path?
  • How to achieve 180 degree exact phase shift?
  • What is significance of ras and cas in SDRAM?
  • Tell some of applications of buffer?
  • Implement an AND gate using mux?
  • What will happen if contents of register are shifter left, right?
  • What is the basic difference between analog and digital design?
  • What advantages do synchronous counters have over asynchronous counters?
  • What types of flip-flops can be used to implement the memory elements of a counter?
  • What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?
  • What is the principal advantage of Gray Code over straight (conventional) binary?
  • What does Pipelining do?
  • Design divide by 2, divide by 3 circuit with equal duty cycle.
  • How many 4:1 mux do you need to design a 8:1 mux?
  • What is D-Word, Q-word?
  • Define Moore, Mealy state machines. Which one is good for timing?
  • Design a FSM to detect 10110. What is the minimum number of flops required?
  • Design a simple circuit based on combinational logic to double the output frequency.
  • Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
  • Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
  • Minimize: S= A' + AB
  • What is the function of a D-flipflop, whose inverted outputs are connected to its input?
  • How to synchronize control signals and data between two different clock domains?
  • Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
  • In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
  • How many bit combinations are there in a byte?
  • What are the different Adder circuits you studied?
  • Give the truth table for a Half Adder. Give a gate level implementation of the same.
  • Convert 65(Hex) to Binary
  • Convert a number to its two's compliment and back.
  • What is the 1's and 2's complement of the decimal number 25.
  • If A?B=C and C?A=B then what is the boolean operator ?