32x8 FIFO

FIFO is nothing but simple queue like we standing in cinema theaters.one who standing first will get ticket last guy may or may not...this is concept.in technical 32x8 fifo is 32 locations with each location can accommodate 8 bit data...in this writeptr and readptr plays very important role...operation starts when write enables data stores into reg and startes incriment writeptr..after completion write operation we have to enable read operation..when read is enabled readptr starts incrimenting and extract data from register....

module fifo2 (dout,enb1, wrtenb, redenb, clk, rst, out,wrtptr,redptr, empty,full);
input enb1;
input [7:0] dout;
input wrtenb;
input redenb;
input clk;
input rst;   
output [4:0] wrtptr;
output [4:0] redptr;
output [7:0] out;
output full;
output empty;
reg [7:0] out;
wire full;
wire empty;
reg [7:0] dreg [0:31] ;
reg [4:0] wrtptr;
reg [4:0] redptr;
always@(posedge clk or negedge rst)
    begin
        if(~rst)
            begin   
            wrtptr<=5'b00000;
            redptr<=5'b00000;
           
            end   
        else  if(enb1)
            if(wrtptr==5'b11111)
                begin
                    wrtptr<=5'b00000;
                   
                end
           
         if(wrtenb==1&&redenb==0)
           
                begin
                   
                     dreg[wrtptr]<=dout;
                    wrtptr<=wrtptr+1;
                end
                if(redptr==5'b11111)
                    begin
                        redptr<=5'b00000;
                       
                        end
                   
              if(wrtenb==0&& redenb==1)
                    begin
                   out <=dreg[redptr];
                  redptr<=redptr+1;
               
                end
            end
       
            assign  full=(wrtptr==5'b11111)?1'b1:1'b0;
            assign empty=(redptr==5'b11111)?1'b1:1'b0;
       endmodule
You could download file 32x8fifo.v and testbench.tb here