VLSI FPGA Design & Verification Questions

1. What is FPGA ?

2. What is the significance of FPGAs in modern day electronics?
3. What is Synthesis?
4. FPGA design flow?
5. Tell me some features of FPGA you are currently using?
6. What is LUT?
7. What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
8. Can you explain what ‘stuck at zero’ means?
9. How to generate clocks on FPGA?
10. What are DCM’s? Why they are used?
11. How do you implement DCM?
12. Why is map-timing option used?
13. What are different types of timing verifications?

14. What is FPGA you are currently using and some of main reasons for choosing it?
15. Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?
16. What is LVs and why do we do that. What is the difference between LVS and DRC?
17. What is minimum and maximum frequency of DCM in spartan-3 series fpga?
18. What is the purpose of a constraint file what is its extension?
19. Tell me some of timing constraints you have used?
20. Can you list out some of synthesizable and non synthesizable constructs?
21. When are DFT and Formal verification used?
22. Can you draw general structure of fpga?
23. What are different types of FPGA programming modes?what are you currently using ?how to change from one to another?
24. How many global buffers are there in your current fpga what is their significance?
25. What is gate count of your project?
26. Can you suggest some ways to increase clock frequency?
27. What is the significance of contamination delay in sequential circuit timing?
28. Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is 50,000 will the size of bitmap change? In other words will size of bitmap change it gate count change?
29. What do conditional assignments get inferred into?
30. What are different types of FPGA programming modes? What are you currently using ? How to change from one to another?
31. What logic is inferred when there are multiple assign statements targeting the same wire?
32. Compare PLL & DLL ?
33. How to achieve 180 degree exact phase shift?
34. We need to sample an input or output something at different rates, but I need to vary the rate? What’s a clean way to do this?
35. What is slice? What is CLB?
36. Can a CLB configured as ram?
37. What is the purpose of DRC?
38. What is frequency of operation and equivalent gate count of u r project?
39. What are the differences between FPGA and CPLD?
40. Draw a rough diagram of how clock is routed through out FPGA?
41. What is DFT ?
42. What is FPGA you are currently using and some of main reasons for choosing it?
43. Draw a rough diagram of how clock is routed through out FPGA?
44. What is SOPC Builder?
45. How do you implement the GCLK when there is lack of Source?
46. What are the latest FPGAs you like?Why?
47. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
48. How do you measure the size and density of various programmable logic devices?
49. What is soft processor? What is hard processor?
50. What is meant by 90nm technology?
51. What are the different forms of pull up?
52. What do you mean by translation and mapping?
53. What do you mean by speed grade?
54. What is the difference between ASIC Design and FPGA Design?
55. Setup time and hold time in digital circuits.
56. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
57. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
58. Knowledge of Synthesis and layout constraints.