UVM Interview Questions Part 1

1.Explain function new and super.build in UVM.
2.Connect virtual interface in driver build_phase.
3.Explain config_db and resource_db.
4.Explain report phase in UVM.
5.Explain raise objection.
6.Explain global stop request.
7.Difference between object and component.
8.Difference between TLM 1.0 and TLM 2.0
9. Difference between Create() and New() ?
10. Can we have user defined phase in UVM?
11. What is analysis port?
12. What is TLM FIFO?
13. How sequence starts?
14. What is the advantage of  'uvm_component_utils() and `uvm_object_utils() ?
15. What is objection?
16. What are the benefits of using UVM?
17. What is the difference between Active mode and Passive mode?
18. What is the difference between copy and clone?
19. What is factory?
20. What are the types of sequencer? Explain each?
21. What are the different phases of uvm_component? Explain each?
22. How set_config_* works?
23. What is super keyword? What is the need of calling super.build() and super.connect()?
24. What is the different between set_config_* and uvm_config_db ?
25. What  are the different  override types?
26. What is virtual sequence and virtual sequencer?
27. Explain end of simulation in UVM?
28. How to declare multiple imports?
29. What is symbolic representation of port, export and analysis port?
30. What is the difference in usage of $finish and global stop request in UVM?
31. What is the difference between `uvm_do and `uvm_ran_send?
32. Why we need to register class with uvm factory?
33. diff between uvm_transaction and uvm_seq_item?
34. can we use set_config and get_config in sequence ?
35. What is uvm_heartbeat ?


some more set questions will be posted very soon.
         

System Verilog Interview Questions Part 1

1.Difference between int and integer.
2.Difference between bit [7:0] and byte.
3.Significance of logic data type?
4.Advantage of using dynamic array?
5.Difference between dynamic array, queue and associative array?
6.Difference between verilog and systemverilog.
7.What is static and dynamic objects in testbench?
8.Why can’t we use interface instead mailbox?
9.What is callback?
10.What is casting? How it works?
11.Explain polymorphism with an example.
12.What is encapsulation?
13.Question regarding stratified event queue how blocking and non-blocking assignments happens in verilog.
14.What is the use of modports?
15.What is input clock skew and output clock skew?
16.Difference between function and task.
17.How to randomize a variable though it is not declared as rand/randc?
18.How this array works arry [*] [$] [ ].
19.features of SV.
20.What is the limitation of randc?
21.Declaring a variable as rand, how to make use of that variable to work as randc.
22.Explain about ignore bins.
23.Explain code coverage.
24. Difference between task and  function?
25. Difference between Final and Initial block?
26. What is Bin?
27. What are void function?
28. What is difference between program and module?
29. What is difference between code coverage and functional coverage?

Digital Design Interview Questions Part 1

1.What is Synthesis?
2.Simplify the equation x' + xy.
3.Design xor gate using muxes.
4.Difference between Mealy and Moore fsm.
5.Design an fsm for sequence detector 1001.
6. A ring counter having 10 pulses .how many flip-flops  needed ?
7. How many minimum number of gates required to implement Half adder ?
   tp =10ns,ts=6ns,th=2ns, calculate clock frequency.

We have covered some more questions in below post.
http://basicsofvlsi.blogspot.in/2011/01/digital-design-interview-questions.html?m=1

Analog Interview Questions Part 1

1. Why do we prefer to use MOSFET over BJTs for VLSI circuits?
2. What are the various regions of operation of MOSFET? How are those regions used?
3. What is threshold voltage?
4. Explain the three regions of operation of a MOSFET.
5. What is channel-length modulation?
6. Explain depletion region?
7. What is body effect?
8. Give various factors on which threshold voltage depends.
9. Give the Cross-sectional diagram of the CMOS.
10. What is the fundamental difference between a MOSFET and BJT ?
11. Why are most interrupts active low?
12. Which is better: synchronous reset or asynchronous reset signal?
13. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
14.What are the important aspects of VLSI optimization?
Power, Area, and Speed.
15.What are the sources of power dissipation?
16.What is the need for power reduction?
17.Give some low power design techniques.
18.Give a disadvantage of voltage scaling technique for power reduction.
19.Give an expression for switching power dissipation.
20.Will glitches in a logic circuit cause power wastage?
21.What is the major source of power wastage in SRAM?
22.What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.