8x1 Multiplexer

It is an combinational device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2ⁿ inputs has n select lines, which are used to select which input line to send to the output.it just acts as switch between devices.....

module mux (s, z, x);
input [2:0] s;
output z;
input [7:0] x;
reg  z;
always @(*)
    begin
        case(s)
            3'b000 :z=x[0];
            3'b001 :z=x[1];
            3'b010 :z=x[2];
            3'b011 :z=x[3];
            3'b100 :z=x[4];
            3'b101 :z=x[5];
            3'b110 :z=x[6];
            3'b111 :z=x[7];
            default: z=1'bz;
        endcase
        end
 endmodule
You could download file mux.v and testbench.tb here

JK Flip-Flop

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

module jkff (j, k, clk, reset, q);
input j;
input k;
input clk;
input reset;
output q;
reg q;
always@(posedge clk or negedge reset)
    begin
    if(~reset)
        begin
            q=1'b0;
        end
    else if(j==1'b0 && k==1'b1)
        begin
            q=1'b0;
        end
     if(j==1'b1 & k==1'b0)
        begin
            q=1'b1;
        end
     if(j==1'b1 & k==1'b1)
        begin
            q=~q;
        end
     if(j==1'b0 & k==1'b0)
        begin
            q=q;
            end
        end
endmodule 
You could download file jkff.v and testbench.tb here.

D Flip-Flop

The D flip-flop is the most common flip-flop in use today. It is better known as delay flip-flop (as its output Q looks like a delay of input D) or data latch.The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low).The D flip-flop can be interpreted as a primitive memory cell.

module dff (data, clk, reset, q);
input data;
input clk;
input reset;
output q;
reg q;
always@(posedge clk)
begin
if(~reset)
begin
q<=1'b0;
end
else
begin
q<=data;
end   
end
endmodule
You could download file dff.v and testbench.tb here.

Basics of vlsi tutorials

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