UVM Interview Questions Part 1

1.Explain function new and super.build in UVM.
2.Connect virtual interface in driver build_phase.
3.Explain config_db and resource_db.
4.Explain report phase in UVM.
5.Explain raise objection.
6.Explain global stop request.
7.Difference between object and component.
8.Difference between TLM 1.0 and TLM 2.0
9. Difference between Create() and New() ?
10. Can we have user defined phase in UVM?
11. What is analysis port?
12. What is TLM FIFO?
13. How sequence starts?
14. What is the advantage of  'uvm_component_utils() and `uvm_object_utils() ?
15. What is objection?
16. What are the benefits of using UVM?
17. What is the difference between Active mode and Passive mode?
18. What is the difference between copy and clone?
19. What is factory?
20. What are the types of sequencer? Explain each?
21. What are the different phases of uvm_component? Explain each?
22. How set_config_* works?
23. What is super keyword? What is the need of calling super.build() and super.connect()?
24. What is the different between set_config_* and uvm_config_db ?
25. What  are the different  override types?
26. What is virtual sequence and virtual sequencer?
27. Explain end of simulation in UVM?
28. How to declare multiple imports?
29. What is symbolic representation of port, export and analysis port?
30. What is the difference in usage of $finish and global stop request in UVM?
31. What is the difference between `uvm_do and `uvm_ran_send?
32. Why we need to register class with uvm factory?
33. diff between uvm_transaction and uvm_seq_item?
34. can we use set_config and get_config in sequence ?
35. What is uvm_heartbeat ?


some more set questions will be posted very soon.