1. Why do we prefer to use MOSFET over BJTs for VLSI circuits?
2. What are the various regions of operation of MOSFET? How are those regions used?
3. What is threshold voltage?
4. Explain the three regions of operation of a MOSFET.
5. What is channel-length modulation?
6. Explain depletion region?
7. What is body effect?
8. Give various factors on which threshold voltage depends.
9. Give the Cross-sectional diagram of the CMOS.
10. What is the fundamental difference between a MOSFET and BJT ?
11. Why are most interrupts active low?
12. Which is better: synchronous reset or asynchronous reset signal?
13. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
14.What are the important aspects of VLSI optimization?
Power, Area, and Speed.
15.What are the sources of power dissipation?
16.What is the need for power reduction?
17.Give some low power design techniques.
18.Give a disadvantage of voltage scaling technique for power reduction.
19.Give an expression for switching power dissipation.
20.Will glitches in a logic circuit cause power wastage?
21.What is the major source of power wastage in SRAM?
22.What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.
2. What are the various regions of operation of MOSFET? How are those regions used?
3. What is threshold voltage?
4. Explain the three regions of operation of a MOSFET.
5. What is channel-length modulation?
6. Explain depletion region?
7. What is body effect?
8. Give various factors on which threshold voltage depends.
9. Give the Cross-sectional diagram of the CMOS.
10. What is the fundamental difference between a MOSFET and BJT ?
11. Why are most interrupts active low?
12. Which is better: synchronous reset or asynchronous reset signal?
13. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
14.What are the important aspects of VLSI optimization?
Power, Area, and Speed.
15.What are the sources of power dissipation?
16.What is the need for power reduction?
17.Give some low power design techniques.
18.Give a disadvantage of voltage scaling technique for power reduction.
19.Give an expression for switching power dissipation.
20.Will glitches in a logic circuit cause power wastage?
21.What is the major source of power wastage in SRAM?
22.What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.
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